From 8fe633449f92d35b60a60de647a4e8fc1b5c8936 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 Nov 2017 14:13:25 -0800 Subject: gpu: nvgpu: Add check_priv_security fuse ops -New fuse ops is added to set NVGPU_SEC_PRIVSECURITY and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags during hal initialization -For igpu non simulation platforms, fuses are read to decide if gpu should be allowed to boot or not. --Do not boot gpu if priv_sec_en is set but wpr_enabled is not set to 1 or vpr_auto_fetch_disable is not set to 0 --With priv_sec_en set, all falcons have to boot in LS mode and this needs wpr_enabled set to 1 AND vpr_auto_fetch_disable set to 0. In this case gmmu tries to pull wpr and vpr settings from tegra mc Bug 2018223 Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1595454 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/fuse_gm20b.c | 90 ++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 drivers/gpu/nvgpu/gm20b/fuse_gm20b.c (limited to 'drivers/gpu/nvgpu/gm20b/fuse_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c new file mode 100644 index 00000000..165d5b43 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c @@ -0,0 +1,90 @@ +/* + * GM20B FUSE + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "fuse_gm20b.h" + +#include + +int gm20b_fuse_check_priv_security(struct gk20a *g) +{ + u32 gcplex_config; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + nvgpu_log(g, gpu_dbg_info, "priv sec is enabled in fmodel"); + return 0; + } + + if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { + nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); + return -EINVAL; + } + + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + + if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { + /* + * all falcons have to boot in LS mode and this needs + * wpr_enabled set to 1 and vpr_auto_fetch_disable + * set to 0. In this case gmmu tries to pull wpr + * and vpr settings from tegra mc + */ + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + if ((gcplex_config & + GCPLEX_CONFIG_WPR_ENABLED_MASK) && + !(gcplex_config & + GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { + if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, " + "secure mode: ACR debug", + gcplex_config); + else + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, " + "secure mode: ACR non debug", + gcplex_config); + } else { + nvgpu_err(g, "gcplex_config = 0x%08x " + "invalid wpr_enabled/vpr_auto_fetch_disable " + "with priv_sec_en", gcplex_config); + /* do not try to boot GPU */ + return -EINVAL; + } + } else { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, non secure mode", + gcplex_config); + } + + return 0; +} -- cgit v1.2.2