From c3c3a3c5715d6aa38544922b76a636135429fd22 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Feb 2017 16:53:35 -0800 Subject: gpu: nvgpu: add fifo ops for handling pbdma intr_0 This is needed to handle bit 20 (clear_faulted_error) and bit 24 (eng_reset) of t19x pbdma_intr_0 interrupt. JIRA GPUT19X-47 Change-Id: I07c603eff96344c0104579e339e5cf7f675128ef Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1306556 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 2f705004..af2a8cd2 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -229,4 +229,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw; gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; + gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; } -- cgit v1.2.2