From 26487b82df0c6604cc40fd6480f7ad7ed4e3efb0 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 1 Jun 2017 13:32:09 +0530 Subject: gpu: nvgpu: move clk_gm20b debugfs to Linux module Move debugfs code from clk_gm20b.c to file in Linux module common/linux/debug_clk.c This file will be compiled only if CONFIG_DEBUG_FS is set Define below new HAL APIs for various clock operations which can be accessed from debug file init_debugfs() get_voltage() get_gpcclk_clock_counter() pll_reg_write() get_pll_debug_data() Export nvgpu_pl_to_div() and nvgpu_div_to_pl() so that these can be accessed from debug_clk.c Add new structure nvgpu_clk_pll_debug_data so that all required register values for debugging can be made available in debug_clk.c Add new API gm20b_get_gpc_pll_parms() so that statically defined variable can be accessed in debug_clk.c too Remove global variable dvfs_safe_max_freq and add it to struct clk_gk20a so that it can accessed from both clk_gm20b.c and debug_clk.c Jira NVGPU-62 Change-Id: I3ae70b40235e78141a686686930e1f178ad59453 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1488903 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 44 +++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index f7912345..1e06d651 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h @@ -21,6 +21,35 @@ #include +struct nvgpu_clk_pll_debug_data { + u32 trim_sys_sel_vco_reg; + u32 trim_sys_sel_vco_val; + + u32 trim_sys_gpc2clk_out_reg; + u32 trim_sys_gpc2clk_out_val; + + u32 trim_sys_bypassctrl_reg; + u32 trim_sys_bypassctrl_val; + + u32 trim_sys_gpcpll_cfg_reg; + u32 trim_sys_gpcpll_dvfs2_reg; + + u32 trim_sys_gpcpll_cfg_val; + bool trim_sys_gpcpll_cfg_enabled; + bool trim_sys_gpcpll_cfg_locked; + bool trim_sys_gpcpll_cfg_sync_on; + + u32 trim_sys_gpcpll_coeff_val; + u32 trim_sys_gpcpll_coeff_mdiv; + u32 trim_sys_gpcpll_coeff_ndiv; + u32 trim_sys_gpcpll_coeff_pldiv; + + u32 trim_sys_gpcpll_dvfs0_val; + u32 trim_sys_gpcpll_dvfs0_dfs_coeff; + u32 trim_sys_gpcpll_dvfs0_dfs_det_max; + u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset; +}; + void gm20b_init_clk_ops(struct gpu_ops *gops); int gm20b_init_clk_setup_sw(struct gk20a *g); @@ -33,5 +62,20 @@ int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate, unsigned long parent_rate); long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate, unsigned long *parent_rate); +struct pll_parms *gm20b_get_gpc_pll_parms(void); +#ifdef CONFIG_DEBUG_FS +int gm20b_clk_init_debugfs(struct gk20a *g); +#endif + +/* 1:1 match between post divider settings and divisor value */ +static inline u32 nvgpu_pl_to_div(u32 pl) +{ + return pl; +} + +static inline u32 nvgpu_div_to_pl(u32 div) +{ + return div; +} #endif /* _NVHOST_CLK_GM20B_H_ */ -- cgit v1.2.2