From 32c6a81258daf155a382526637c84925dc52022c Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 4 Aug 2017 20:03:22 -0700 Subject: gpu: nvgpu: Update GM20B GPCPLL rev C1 parameters - Set GM20B GPCPLL rev C1 DFS coefficients. - Updated VCO control setting - Decreased output frequency minimum to 76.8 MHz Bug 1971441 Change-Id: Ie1fa04db11d9cd76db0424acd9f24c02c6e6054a Signed-off-by: Alex Frid Reviewed-on: https://git-master.nvidia.com/r/1533493 (cherry picked from commit cc495b86ad97a0a713fd46f74a4fd6d17336ff02) Reviewed-on: https://git-master.nvidia.com/r/1538242 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 027d4fb6..81f8aec0 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -59,15 +59,15 @@ static struct pll_parms gpc_pll_params_b1 = { }; static struct pll_parms gpc_pll_params_c1 = { - 128000, 2600000, /* freq */ + 76800, 2600000, /* freq */ 1300000, 2600000, /* vco */ 19200, 38400, /* u */ 1, 255, /* M */ 8, 255, /* N */ 1, 31, /* PL */ - 0, 0, /* DFS_COEFF */ + -172550, 195374, /* DFS_COEFF */ 0, 0, /* ADC char coeff - to be read from fuses */ - 0x7 << 3, /* vco control in NA mode */ + (0x1 << 3) | 0x7, /* vco control in NA mode */ 500, /* Locking and ramping timeout */ 40, /* Lock delay in NA mode */ 5, /* IDDQ mode exit delay */ -- cgit v1.2.2