From 09cc99d33dbd593981974104fdfc67213b9d2916 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 17 Oct 2014 19:31:56 -0700 Subject: gpu: nvgpu: Protect GM20b clock init from div-by-0 Protected GM20b clock initialization from div-by-0 in case when safe fmax at Vmin is not known, and the respective interface returns zero. Change-Id: I2064a3182c93f283c7e85c247601203dd1f71af4 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/559059 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 7229e168..29a47f7c 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -1109,10 +1109,10 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) clk_get_parent(clk->tegra_clk)); safe_rate = safe_rate * (100 - DVFS_SAFE_MARGIN) / 100; dvfs_safe_max_freq = rate_gpu_to_gpc2clk(safe_rate); - clk->gpc_pll.PL = DIV_ROUND_UP(gpc_pll_params.min_vco, - dvfs_safe_max_freq); + clk->gpc_pll.PL = (dvfs_safe_max_freq == 0) ? 0 : + DIV_ROUND_UP(gpc_pll_params.min_vco, dvfs_safe_max_freq); - /* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */ + /* Initial freq: low enough to be safe at Vmin (default 1/3 VCO min) */ clk->gpc_pll.M = 1; clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco, clk->gpc_pll.clk_in); -- cgit v1.2.2