From b7793a493a1fa292a22d5ce84c43ee342b9824b2 Mon Sep 17 00:00:00 2001 From: Supriya Date: Fri, 13 Jun 2014 12:44:27 +0530 Subject: nvgpu: Host side changes to support HS mode GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal Reviewed-by: Deepak Nibade Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 377 ++++++++++++++++++++++++++++++++++++ 1 file changed, 377 insertions(+) create mode 100644 drivers/gpu/nvgpu/gm20b/acr_gm20b.h (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h new file mode 100644 index 00000000..e0dd50d0 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h @@ -0,0 +1,377 @@ +/* + * GM20B ACR + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ACR_GM20B_H_ +#define __ACR_GM20B_H_ +#include "gk20a/gk20a.h" +#include "mm_gm20b.h" + +/*Defines*/ + +/*chip specific defines*/ +#define MAX_SUPPORTED_LSFM 1 /*PMU, FECS, GPCCS*/ +#define LSF_UCODE_DATA_ALIGNMENT 4096 + +#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode.bin" +#define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin" +#define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin" + +#define LSFM_DISABLE_MASK_NONE (0x00000000) /*Disable all LS falcons*/ +#define LSFM_DISABLE_MASK_ALL (0xFFFFFFFF) /*Enable all LS falcons*/ + +#define PMU_SECURE_MODE (0x1) +#define PMU_LSFM_MANAGED (0x2) + +/*ACR load related*/ +/*! + * Supporting maximum of 2 regions. + * This is needed to pre-allocate space in DMEM + */ +#define T210_FLCN_ACR_MAX_REGIONS (2) +#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) + +/*! + * Falcon Id Defines + * Defines a common Light Secure Falcon identifier. + */ +#define LSF_FALCON_ID_PMU (0) +#define LSF_FALCON_ID_FECS (2) +#define LSF_FALCON_ID_GPCCS (3) +#define LSF_FALCON_ID_INVALID (0xFFFFFFFF) + +/*! + * Bootstrap Owner Defines + */ +#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU) + +/*! + * Image Status Defines + */ +#define LSF_IMAGE_STATUS_NONE (0) +#define LSF_IMAGE_STATUS_COPY (1) +#define LSF_IMAGE_STATUS_VALIDATION (2) +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (3) + +/*LSB header related defines*/ +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4 + +/*! + * Light Secure WPR Content Alignments + */ +#define LSF_LSB_HEADER_ALIGNMENT 256 +#define LSF_BL_DATA_ALIGNMENT 256 +#define LSF_BL_DATA_SIZE_ALIGNMENT 256 +#define LSF_BL_CODE_SIZE_ALIGNMENT 256 + +/*! + * Falcon UCODE header index. + */ +#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0) +#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1) +#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2) +#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3) +#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4) +/*! + * There are total N number of Apps with code and offset defined in UCODE header + * This macro provides the CODE and DATA offset and size of Ath application. + */ +#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5) +#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2)) +#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1) +#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1) + +#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1) +#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2)) +#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1) +#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1) + +#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1) +#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) + +/*Externs*/ + +/*Structs*/ + +/*! + * Light Secure Falcon Ucode Description Defines + * This stucture is prelim and may change as the ucode signing flow evolves. + */ +struct lsf_ucode_desc { + u8 prd_keys[2][16]; + u8 dbg_keys[2][16]; + u32 b_prd_present; + u32 b_dbg_present; + u32 falcon_id; +}; + +/*! + * Light Secure WPR Header + * Defines state allowing Light Secure Falcon bootstrapping. + * + * falcon_id - LS falcon ID + * lsb_offset - Offset into WPR region holding LSB header + * bootstrap_owner - Bootstrap OWNER (either PMU or SEC2) + * lazy_bootstrap - Skip bootstrapping by ACR + * status - Bootstrapping status + */ +struct lsf_wpr_header { + u32 falcon_id; + u32 lsb_offset; + u32 bootstrap_owner; + u32 lazy_bootstrap; + u32 status; +}; + +struct lsf_lsb_header { + struct lsf_ucode_desc signature; + u32 ucode_off; + u32 ucode_size; + u32 data_size; + u32 bl_code_size; + u32 bl_imem_off; + u32 bl_data_off; + u32 bl_data_size; + u32 flags; +}; + +/*! + * Structure used by the boot-loader to load the rest of the code. This has + * to be filled by host and copied into DMEM at offset provided in the + * hsflcn_bl_desc.bl_desc_dmem_load_off. + * + * signature - 16B signature for secure code. 0s if no secure code + * ctx_dma - CtxDma to be used by BL while loading code/data + * code_dma_base - 256B aligned Physical FB Address where code is located + * non_sec_code_off - Offset from code_dma_base where the nonSecure code is + * located. The offset must be multiple of 256 to help perf + * non_sec_code_size - The size of the nonSecure code part. + * sec_code_size - Offset from code_dma_base where the secure code is + * located. The offset must be multiple of 256 to help perf + * code_entry_point - Code entry point which will be invoked by BL after + * code is loaded. + * data_dma_base - 256B aligned Physical FB Address where data is located. + * data_size - Size of data block. Should be multiple of 256B + */ +struct flcn_bl_dmem_desc { + u32 signature[4]; /*Should be the first element..*/ + u32 ctx_dma; + u32 code_dma_base; + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + u32 data_dma_base; + u32 data_size; +}; + +/*! + * Legacy structure used by the current PMU/DPU bootloader. + */ +struct loader_config { + u32 dma_idx; + u32 code_dma_base; /*