From 5d30a5cda37ca349b4d9cb7e1985c7a0849001b6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 6 Sep 2018 20:44:27 +0530 Subject: gpu: nvgpu: ACR code refactor -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 329d53b8..cae6ab6a 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h @@ -37,21 +37,32 @@ bool gm20b_is_pmu_supported(struct gk20a *g); int prepare_ucode_blob(struct gk20a *g); bool gm20b_is_lazy_bootstrap(u32 falcon_id); bool gm20b_is_priv_load(u32 falcon_id); -void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); -int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct nvgpu_mem *mem); int gm20b_pmu_populate_loader_cfg(struct gk20a *g, void *lsfm, u32 *p_bl_gen_desc_size); int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); void gm20b_update_lspmu_cmdline_args(struct gk20a *g); void gm20b_setup_apertures(struct gk20a *g); - int gm20b_pmu_setup_sw(struct gk20a *g); int gm20b_init_nspmu_setup_hw1(struct gk20a *g); + int acr_ucode_patch_sig(struct gk20a *g, unsigned int *p_img, unsigned int *p_prod_sig, unsigned int *p_dbg_sig, unsigned int *p_patch_loc, unsigned int *p_patch_ind); +int gm20b_alloc_blob_space(struct gk20a *g, + size_t size, struct nvgpu_mem *mem); +void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); +int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g, + struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery); +int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g, + struct nvgpu_acr *acr, struct hs_acr *acr_desc, + u32 *acr_ucode_header); +int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr, + struct hs_acr *acr_desc); +void gm20b_remove_acr_support(struct nvgpu_acr *acr); +void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); + #endif /*NVGPU_GM20B_ACR_GM20B_H*/ -- cgit v1.2.2