From 6299b00beb9dabdd53c211b02658d022827b3232 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 2 Jun 2016 09:34:46 +0530 Subject: gpu: nvgpu: Add multiple engine and runlist support This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt handling support for gm206 GPU family 5) Added generic mechanism to identify the CE engine pri_base address for gm206 (CE0, CE1 and CE2) 6) Removed hard coded engine_id logic and made generic way 7) Code cleanup for readability JIRA DNVGPU-26 Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1155963 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gm206/ce_gm206.c | 107 ++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gm206/ce_gm206.h | 26 ++++++++ drivers/gpu/nvgpu/gm206/fifo_gm206.c | 2 + drivers/gpu/nvgpu/gm206/hal_gm206.c | 7 ++- drivers/gpu/nvgpu/gm206/hw_proj_gm206.h | 4 ++ drivers/gpu/nvgpu/gm206/hw_top_gm206.h | 16 +++++ 6 files changed, 160 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gm206/ce_gm206.c create mode 100644 drivers/gpu/nvgpu/gm206/ce_gm206.h (limited to 'drivers/gpu/nvgpu/gm206') diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.c b/drivers/gpu/nvgpu/gm206/ce_gm206.c new file mode 100644 index 00000000..9ec42831 --- /dev/null +++ b/drivers/gpu/nvgpu/gm206/ce_gm206.c @@ -0,0 +1,107 @@ +/* + * GM206 Copy Engine. + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ + +/*TODO: remove uncecessary */ +#include "gk20a/gk20a.h" +#include "ce_gm206.h" + +/*TODO: remove uncecessary */ +#include +#include +#include +#include +#include +#include + +#include "gk20a/debug_gk20a.h" +#include "gk20a/semaphore_gk20a.h" +#include "hw_ce2_gm206.h" +#include "hw_pbdma_gm206.h" +#include "hw_ccsr_gm206.h" +#include "hw_ram_gm206.h" +#include "hw_top_gm206.h" +#include "hw_mc_gm206.h" +#include "hw_gr_gm206.h" + +/* TODO: We need generic way for query the intr_status register offset. + * As of now, there is no way to query this information from dev_ceN_pri.h */ +#define COP_INTR_STATUS_OFFSET 0x908 + +static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) +{ + gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n"); + + return ce2_intr_status_nonblockpipe_pending_f(); +} + +static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) +{ + gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); + + return ce2_intr_status_blockpipe_pending_f(); +} + +static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) +{ + gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n"); + + return ce2_intr_status_launcherr_pending_f(); +} + +void gm206_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +{ + u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); + u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); + u32 clear_intr = 0; + + gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); + + /* clear blocking interrupts: they exibit broken behavior */ + if (ce_intr & ce2_intr_status_blockpipe_pending_f()) + clear_intr |= ce_blockpipe_isr(g, ce_intr, inst_id); + + if (ce_intr & ce2_intr_status_launcherr_pending_f()) + clear_intr |= ce_launcherr_isr(g, ce_intr, inst_id); + + gk20a_writel(g, ce_intr_status_reg, clear_intr); + return; +} + +void gm206_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +{ + u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); + u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); + + gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); + + if (ce_intr & ce2_intr_status_nonblockpipe_pending_f()) { + gk20a_writel(g, ce_intr_status_reg, + ce_nonblockpipe_isr(g, ce_intr, inst_id)); + + /* wake threads waiting in this channel */ + gk20a_channel_semaphore_wakeup(g, true); + } + + return; +} + +void gm206_init_ce(struct gpu_ops *gops) +{ + gops->ce2.isr_stall = gm206_ce_isr; + gops->ce2.isr_nonstall = gm206_ce_nonstall_isr; +} diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.h b/drivers/gpu/nvgpu/gm206/ce_gm206.h new file mode 100644 index 00000000..c2fb1586 --- /dev/null +++ b/drivers/gpu/nvgpu/gm206/ce_gm206.h @@ -0,0 +1,26 @@ +/* + * GM206 copy engine. + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ +#ifndef __CE_GM206_H__ +#define __CE_GM206_H__ + +#include "gk20a/channel_gk20a.h" +#include "gk20a/tsg_gk20a.h" + +void gm206_init_ce(struct gpu_ops *gops); + +#endif /*__CE2_GM20B_H__*/ diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.c b/drivers/gpu/nvgpu/gm206/fifo_gm206.c index c78f256c..6caf30f4 100644 --- a/drivers/gpu/nvgpu/gm206/fifo_gm206.c +++ b/drivers/gpu/nvgpu/gm206/fifo_gm206.c @@ -18,6 +18,7 @@ #include "gm20b/fifo_gm20b.h" #include "fifo_gm206.h" #include "hw_ccsr_gm206.h" +#include "hw_fifo_gm206.h" static u32 gm206_fifo_get_num_fifos(struct gk20a *g) { @@ -28,4 +29,5 @@ void gm206_init_fifo(struct gpu_ops *gops) { gm20b_init_fifo(gops); gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos; + gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; } diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c index 048a109f..6b5c70e2 100644 --- a/drivers/gpu/nvgpu/gm206/hal_gm206.c +++ b/drivers/gpu/nvgpu/gm206/hal_gm206.c @@ -21,7 +21,7 @@ #include "gm20b/mc_gm20b.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/mm_gm20b.h" -#include "gm20b/ce2_gm20b.h" +#include "ce_gm206.h" #include "gm20b/fb_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -142,6 +142,9 @@ static int gm206_get_litter_value(struct gk20a *g, case GPU_LIT_ROP_SHARED_BASE: ret = proj_rop_shared_base_v(); break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; case GPU_LIT_HOST_NUM_PBDMA: ret = proj_host_num_pbdma_v(); break; @@ -183,7 +186,7 @@ int gm206_init_hal(struct gk20a *g) gm20b_init_fb(gops); g->ops.fb.set_use_full_comp_tag_line = NULL; gm206_init_fifo(gops); - gm20b_init_ce2(gops); + gm206_init_ce(gops); gm20b_init_gr_ctx(gops); gm20b_init_mm(gops); gm206_init_pmu_ops(gops); diff --git a/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h index 2f4187d0..6c21b39a 100644 --- a/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h +++ b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h @@ -106,6 +106,10 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) { return 0x00001800; } +static inline u32 proj_host_num_engines_v(void) +{ + return 0x00000008; +} static inline u32 proj_host_num_pbdma_v(void) { return 0x00000003; diff --git a/drivers/gpu/nvgpu/gm206/hw_top_gm206.h b/drivers/gpu/nvgpu/gm206/hw_top_gm206.h index e6ec1d27..988f24ea 100644 --- a/drivers/gpu/nvgpu/gm206/hw_top_gm206.h +++ b/drivers/gpu/nvgpu/gm206/hw_top_gm206.h @@ -146,6 +146,22 @@ static inline u32 top_device_info_type_enum_copy0_f(void) { return 0x4; } +static inline u32 top_device_info_type_enum_copy1_v(void) +{ + return 0x00000002; +} +static inline u32 top_device_info_type_enum_copy1_f(void) +{ + return 0x8; +} +static inline u32 top_device_info_type_enum_copy2_v(void) +{ + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} static inline u32 top_device_info_entry_v(u32 r) { return (r >> 0) & 0x3; -- cgit v1.2.2