From edb116661348f1bc843849cdcc318fa47cf9724a Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 16 Aug 2017 16:19:53 -0700 Subject: gpu: nvgpu: rename ops.mm.get_physical_addr_bits Rename get_physical_addr_bits and related functions to something that more clearly conveys what they are doing. The basic idea of these functions is to translate from a physical GPU address to a IOMMU GPU address. To do that a particular bit (that varies from chip to chip) is added to the physical address. JIRA NVGPU-68 Change-Id: I536cc595c4397aad69a24f740bc74db03f52bc0a Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1542966 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 13 +------------ drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 4 +--- 3 files changed, 3 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8dabee63..db38fae4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -741,7 +741,7 @@ struct gpu_ops { struct nvgpu_mem *mem, int size); u32 (*get_big_page_sizes)(void); u32 (*get_default_big_page_size)(void); - u32 (*get_physical_addr_bits)(struct gk20a *g); + u32 (*get_iommu_bit)(struct gk20a *g); int (*init_mm_setup_hw)(struct gk20a *g); bool (*is_bar1_supported)(struct gk20a *g); int (*init_bar2_vm)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 3d1f8d28..795f7bda 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -1271,17 +1271,6 @@ dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr) return addr; } -u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, u64 iova) -{ - /* ensure it is not vidmem allocation */ - WARN_ON(is_vidmem_page_alloc(iova)); - - if (nvgpu_iommuable(g) && g->ops.mm.get_physical_addr_bits) - return iova | 1ULL << g->ops.mm.get_physical_addr_bits(g); - - return iova; -} - /* for gk20a the "video memory" apertures here are misnomers. */ static inline u32 big_valid_pde0_bits(struct gk20a *g, struct nvgpu_gmmu_pd *pd, u64 addr) @@ -2170,7 +2159,7 @@ int gk20a_mm_suspend(struct gk20a *g) return 0; } -u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g) +u32 gk20a_mm_get_iommu_bit(struct gk20a *g) { return 34; } diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 13a3dcd0..9f03a495 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h @@ -342,8 +342,6 @@ void gk20a_mm_dump_vm(struct vm_gk20a *vm, int gk20a_mm_suspend(struct gk20a *g); -u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova); - void gk20a_mm_ltc_isr(struct gk20a *g); bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g); @@ -420,7 +418,7 @@ void pde_range_from_vaddr_range(struct vm_gk20a *vm, u64 addr_lo, u64 addr_hi, u32 *pde_lo, u32 *pde_hi); int gk20a_mm_pde_coverage_bit_count(struct vm_gk20a *vm); -u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g); +u32 gk20a_mm_get_iommu_bit(struct gk20a *g); const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, u32 big_page_size); -- cgit v1.2.2