From e9d5e7dfca6ac2fa7af380ceea0a0ca4ac3827c6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 23 May 2016 16:12:11 +0530 Subject: gpu: nvgpu: secure boot HAL update Updated/added secure boot HAL with methods required to support multiple GPU chips. JIRA DNVGPU-10 Change-Id: I343b289f2236fd6a6b0ecf9115367ce19990e7d5 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1151784 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 19 +++++++++++++++++++ drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 13 +++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d131862b..d96ce3d8 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -534,6 +534,25 @@ struct gpu_ops { (struct gk20a *g, u32 mask); void (*dump_secure_fuses)(struct gk20a *g); int (*reset)(struct gk20a *g); + int (*falcon_wait_for_halt)(struct gk20a *g, + unsigned int timeout); + int (*falcon_clear_halt_interrupt_status)(struct gk20a *g, + unsigned int timeout); + int (*init_falcon_setup_hw)(struct gk20a *g, + struct flcn_bl_dmem_desc *desc, u32 bl_sz); + bool (*is_lazy_bootstrap)(u32 falcon_id); + bool (*is_priv_load)(u32 falcon_id); + void (*get_wpr)(struct gk20a *g, u64 *base, u64 *size); + int (*alloc_blob_space)(struct gk20a *g, + size_t size, struct mem_desc *mem); + int (*pmu_populate_loader_cfg)(struct gk20a *g, + struct lsfm_managed_ucode_img *lsfm, + union flcn_bl_generic_desc *p_bl_gen_desc, + u32 *p_bl_gen_desc_size); + int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, + struct lsfm_managed_ucode_img *lsfm, + union flcn_bl_generic_desc *p_bl_gen_desc, + u32 *p_bl_gen_desc_size, u32 falconid); u32 lspmuwprinitdone; u32 lsfloadedfalconid; bool fecsbootstrapdone; diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 08ef7738..a8ebaf7a 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -2758,9 +2758,12 @@ static void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) int gk20a_pmu_reset(struct gk20a *g) { - gk20a_reset(g, mc_enable_pwr_enabled_f()); + int err; + struct pmu_gk20a *pmu = &g->pmu; - return 0; + err = pmu_reset(pmu); + + return err; } void gk20a_init_pmu_ops(struct gpu_ops *gops) @@ -2776,6 +2779,12 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_pg_grinit_param = NULL; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; gops->pmu.dump_secure_fuses = NULL; + gops->pmu.is_lazy_bootstrap = NULL; + gops->pmu.is_priv_load = NULL; + gops->pmu.get_wpr = NULL; + gops->pmu.alloc_blob_space = NULL; + gops->pmu.pmu_populate_loader_cfg = NULL; + gops->pmu.flcn_populate_bl_dmem_desc = NULL; gops->pmu.reset = gk20a_pmu_reset; } -- cgit v1.2.2