From e2148ead8bbf51c2dbf9e2b501c989f2c27582a0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 1 May 2017 18:32:46 -0700 Subject: gpu: nvgpu: Program CE clock gating list after reset Clock gating list for CE was programmed at GR init, but at that time CE has not yet been brought out of reset. This causes a priv ring error and the clock gating setting does not take place. Move programming of CE clock gating list to CE initialization. Bug 1846641 Change-Id: Ibc9fe2487408358304f80cd679d3b1ecac7cebe8 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1473301 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 12 ++++++++++++ drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 3 --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 9 +-------- 3 files changed, 13 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index ed5a8b4e..8e3f1754 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c @@ -339,6 +339,18 @@ int gk20a_init_ce_support(struct gk20a *g) { struct gk20a_ce_app *ce_app = &g->ce_app; int err; + u32 ce_reset_mask; + + ce_reset_mask = gk20a_fifo_get_all_ce_engine_reset_mask(g); + + g->ops.mc.reset(g, ce_reset_mask); + + if (g->ops.clock_gating.slcg_ce2_load_gating_prod) + g->ops.clock_gating.slcg_ce2_load_gating_prod(g, + g->slcg_enabled); + if (g->ops.clock_gating.blcg_ce_load_gating_prod) + g->ops.clock_gating.blcg_ce_load_gating_prod(g, + g->blcg_enabled); if (ce_app->initialised) { /* assume this happen during poweron/poweroff GPU sequence */ diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 4129e407..cb54a1ca 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -767,9 +767,6 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) /* enable pmc pfifo */ g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); - if (g->ops.clock_gating.slcg_ce2_load_gating_prod) - g->ops.clock_gating.slcg_ce2_load_gating_prod(g, - g->slcg_enabled); if (g->ops.clock_gating.slcg_fifo_load_gating_prod) g->ops.clock_gating.slcg_fifo_load_gating_prod(g, g->slcg_enabled); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index b2225dae..48becc81 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -4935,9 +4935,6 @@ static void gr_gk20a_load_gating_prod(struct gk20a *g) if (g->ops.clock_gating.blcg_bus_load_gating_prod) g->ops.clock_gating.blcg_bus_load_gating_prod(g, g->blcg_enabled); - if (g->ops.clock_gating.blcg_ce_load_gating_prod) - g->ops.clock_gating.blcg_ce_load_gating_prod(g, - g->blcg_enabled); if (g->ops.clock_gating.blcg_gr_load_gating_prod) g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled); @@ -4957,9 +4954,6 @@ static int gk20a_init_gr_prepare(struct gk20a *g) { u32 gpfifo_ctrl, pmc_en; u32 err = 0; - u32 ce_reset_mask; - - ce_reset_mask = gk20a_fifo_get_all_ce_engine_reset_mask(g); /* disable fifo access */ pmc_en = gk20a_readl(g, mc_enable_r()); @@ -4972,8 +4966,7 @@ static int gk20a_init_gr_prepare(struct gk20a *g) /* reset gr engine */ g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() | mc_enable_blg_enabled_f() | - mc_enable_perfmon_enabled_f() | - ce_reset_mask); + mc_enable_perfmon_enabled_f()); gr_gk20a_load_gating_prod(g); -- cgit v1.2.2