From c218fefe848893c9e4fa6b44ac65439444e47b04 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 16 Feb 2017 09:29:15 -0800 Subject: gpu: nvgpu: Fix unicast register accesses for SM In two places we used broadcast register as base, but added the unicast offset to it. This causes the write to go well beyond valid register range. Change the broadcast base to use unicast base instead in sequence to resume a single SM and to record error state of SM. Bug 200256272 Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2 Signed-off-by: Terje Bergstrom (cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c) Reviewed-on: http://git-master/r/1306331 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 170bfc7f..d3b91a50 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -8740,7 +8740,7 @@ void gk20a_resume_single_sm(struct gk20a *g, gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(), gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f()); gk20a_writel(g, - gr_gpcs_tpcs_sm_dbgr_control0_r() + offset, dbgr_control0); + gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); /* Run trigger */ dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(); -- cgit v1.2.2