From bbef4c6927a13a24821c43cb2b6af72f859f7deb Mon Sep 17 00:00:00 2001 From: David Ung Date: Fri, 24 Apr 2020 17:46:15 -0700 Subject: gpu: nvgpu: initialize masks for the perfmon counters 3 Initialize the perfmon counters #3 masks to be same values as ELPG. Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030, but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0. Bug 2833620 Change-Id: I3a424345aec6176a97dd20fb2c68a6e2faf955ad Signed-off-by: David Ung Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299 Reviewed-by: automaticguardword Reviewed-by: Alex Waterman Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 050423b0..63a32f03 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -760,6 +760,10 @@ void gk20a_pmu_init_perfmon_counter(struct gk20a *g) pwr_pmu_idle_mask_gr_enabled_f() | pwr_pmu_idle_mask_ce_2_enabled_f()); + /* assign same mask setting from GR ELPG to counter #3 */ + data = gk20a_readl(g, pwr_pmu_idle_mask_1_supp_r(0)); + gk20a_writel(g, pwr_pmu_idle_mask_1_r(3), data); + /* disable idle filtering for counters 3 and 6 */ data = gk20a_readl(g, pwr_pmu_idle_ctrl_r(3)); data = set_field(data, pwr_pmu_idle_ctrl_value_m() | -- cgit v1.2.2