From b7793a493a1fa292a22d5ce84c43ee342b9824b2 Mon Sep 17 00:00:00 2001 From: Supriya Date: Fri, 13 Jun 2014 12:44:27 +0530 Subject: nvgpu: Host side changes to support HS mode GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal Reviewed-by: Deepak Nibade Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gk20a/gk20a.h | 9 +++++++++ drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 2 ++ drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 37 +++++++++++++++++++++++++------------ drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 17 ++++++++++++++++- 4 files changed, 52 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 726994ff..da5cc917 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -28,6 +28,7 @@ struct channel_gk20a; struct gr_gk20a; struct sim_gk20a; struct gk20a_ctxsw_ucode_segments; +struct acr_gm20b; #include #include @@ -45,6 +46,7 @@ struct gk20a_ctxsw_ucode_segments; #include "priv_ring_gk20a.h" #include "therm_gk20a.h" #include "platform_gk20a.h" +#include "gm20b/acr_gm20b.h" extern struct platform_device tegra_gk20a_device; @@ -205,6 +207,8 @@ struct gpu_ops { struct pmu_sequence *seq); void *(*get_pmu_seq_out_a_ptr)( struct pmu_sequence *seq); + void (*set_pmu_cmdline_args_secure_mode)(struct pmu_gk20a *pmu, + u32 val); } pmu_ver; struct { int (*get_netlist_name)(int index, char *name); @@ -214,6 +218,10 @@ struct gpu_ops { int (*set_sparse)(struct vm_gk20a *vm, u64 vaddr, u32 num_pages, u32 pgsz_idx); } mm; + struct { + int (*pmu_setup_sw)(struct gk20a *g); + int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); + } pmu; }; struct gk20a { @@ -236,6 +244,7 @@ struct gk20a { struct sim_gk20a sim; struct mm_gk20a mm; struct pmu_gk20a pmu; + struct acr_gm20b acr; struct cooling_device_gk20a gk20a_cdev; /* Save pmu fw here so that it lives cross suspend/resume. diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 66bc47a9..ad0a3dc7 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c @@ -23,6 +23,7 @@ #include "channel_gk20a.h" #include "gr_ctx_gk20a.h" #include "mm_gk20a.h" +#include "pmu_gk20a.h" struct gpu_ops gk20a_ops = { .clock_gating = { @@ -48,6 +49,7 @@ int gk20a_init_hal(struct gpu_ops *gops) gk20a_init_fifo(gops); gk20a_init_gr_ctx(gops); gk20a_init_mm(gops); + gk20a_init_pmu_ops(gops); gops->name = "gk20a"; return 0; diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index b784b9a6..9b1ecea1 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -38,10 +38,8 @@ #define gk20a_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) -static void pmu_dump_falcon_stats(struct pmu_gk20a *pmu); static int gk20a_pmu_get_elpg_residency_gating(struct gk20a *g, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); -static void pmu_setup_hw(struct work_struct *work); static void ap_callback_init_and_enable_ctrl( struct gk20a *g, struct pmu_msg *msg, void *param, u32 seq_desc, u32 status); @@ -62,6 +60,10 @@ static void set_pmu_cmdline_args_cpufreq_v1(struct pmu_gk20a *pmu, u32 freq) { pmu->args_v1.cpu_freq_hz = freq; } +static void set_pmu_cmdline_args_secure_mode_v1(struct pmu_gk20a *pmu, u32 val) +{ + pmu->args_v1.secure_mode = val; +} static void set_pmu_cmdline_args_cpufreq_v0(struct pmu_gk20a *pmu, u32 freq) { @@ -482,10 +484,12 @@ static void *get_pmu_sequence_out_alloc_ptr_v0(struct pmu_sequence *seq) return (void *)(&seq->out_v0); } -static int gk20a_init_pmu(struct pmu_gk20a *pmu) +int gk20a_init_pmu(struct pmu_gk20a *pmu) { struct gk20a *g = pmu->g; switch (pmu->desc->app_version) { + case APP_VERSION_GM20B_1: + case APP_VERSION_GM20B: case APP_VERSION_1: case APP_VERSION_2: g->ops.pmu_ver.cmd_id_zbc_table_update = 16; @@ -493,6 +497,8 @@ static int gk20a_init_pmu(struct pmu_gk20a *pmu) pmu_cmdline_size_v1; g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = set_pmu_cmdline_args_cpufreq_v1; + g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = + set_pmu_cmdline_args_secure_mode_v1; g->ops.pmu_ver.get_pmu_cmdline_args_ptr = get_pmu_cmdline_args_ptr_v1; g->ops.pmu_ver.get_pmu_allocation_struct_size = @@ -558,6 +564,8 @@ static int gk20a_init_pmu(struct pmu_gk20a *pmu) pmu_cmdline_size_v0; g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = set_pmu_cmdline_args_cpufreq_v0; + g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = + NULL; g->ops.pmu_ver.get_pmu_cmdline_args_ptr = get_pmu_cmdline_args_ptr_v0; g->ops.pmu_ver.get_pmu_allocation_struct_size = @@ -627,7 +635,7 @@ static int gk20a_init_pmu(struct pmu_gk20a *pmu) return 0; } -static void pmu_copy_from_dmem(struct pmu_gk20a *pmu, +void pmu_copy_from_dmem(struct pmu_gk20a *pmu, u32 src, u8 *dst, u32 size, u8 port) { struct gk20a *g = pmu->g; @@ -673,7 +681,7 @@ static void pmu_copy_from_dmem(struct pmu_gk20a *pmu, return; } -static void pmu_copy_to_dmem(struct pmu_gk20a *pmu, +void pmu_copy_to_dmem(struct pmu_gk20a *pmu, u32 dst, u8 *src, u32 size, u8 port) { struct gk20a *g = pmu->g; @@ -887,7 +895,7 @@ static int pmu_enable(struct pmu_gk20a *pmu, bool enable) return 0; } -static int pmu_reset(struct pmu_gk20a *pmu) +int pmu_reset(struct pmu_gk20a *pmu) { int err; @@ -999,7 +1007,7 @@ static int pmu_bootstrap(struct pmu_gk20a *pmu) return 0; } -static void pmu_seq_init(struct pmu_gk20a *pmu) +void pmu_seq_init(struct pmu_gk20a *pmu) { u32 i; @@ -1784,7 +1792,7 @@ static int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id); static void pmu_setup_hw_load_zbc(struct gk20a *g); static void pmu_setup_hw_enable_elpg(struct gk20a *g); -static void pmu_setup_hw(struct work_struct *work) +void pmu_setup_hw(struct work_struct *work) { struct pmu_gk20a *pmu = container_of(work, struct pmu_gk20a, pg_init); struct gk20a *g = pmu->g; @@ -1967,6 +1975,12 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) } } +void gk20a_init_pmu_ops(struct gpu_ops *gops) +{ + gops->pmu.pmu_setup_sw = gk20a_init_pmu_setup_sw; + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; +} + int gk20a_init_pmu_support(struct gk20a *g) { struct pmu_gk20a *pmu = &g->pmu; @@ -1984,11 +1998,10 @@ int gk20a_init_pmu_support(struct gk20a *g) return err; if (support_gk20a_pmu()) { - err = gk20a_init_pmu_setup_sw(g); + err = g->ops.pmu.pmu_setup_sw(g); if (err) return err; - - err = gk20a_init_pmu_setup_hw1(g); + err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g); if (err) return err; } @@ -2724,7 +2737,7 @@ static void pmu_dump_elpg_stats(struct pmu_gk20a *pmu) */ } -static void pmu_dump_falcon_stats(struct pmu_gk20a *pmu) +void pmu_dump_falcon_stats(struct pmu_gk20a *pmu) { struct gk20a *g = pmu->g; int i; diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 2843d483..e9567e14 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -51,6 +51,8 @@ /* Mapping between AP_CTRLs and Idle counters */ #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) +#define APP_VERSION_GM20B_1 18547257 +#define APP_VERSION_GM20B 17615280 #define APP_VERSION_2 18542378 #define APP_VERSION_1 17997577 #define APP_VERSION_0 16856675 @@ -1058,6 +1060,8 @@ struct pmu_gk20a { }; unsigned long perfmon_events_cnt; bool perfmon_sampling_enabled; + u8 pmu_mode; /*Added for GM20b, and ACR*/ + u32 falcon_id; }; int gk20a_init_pmu_support(struct gk20a *g); @@ -1086,5 +1090,16 @@ int gk20a_pmu_debugfs_init(struct platform_device *dev); void gk20a_pmu_reset_load_counters(struct gk20a *g); void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, u32 *total_cycles); - +void gk20a_init_pmu_ops(struct gpu_ops *gops); + +void pmu_copy_to_dmem(struct pmu_gk20a *pmu, + u32 dst, u8 *src, u32 size, u8 port); +void pmu_copy_from_dmem(struct pmu_gk20a *pmu, + u32 src, u8 *dst, u32 size, u8 port); +int pmu_reset(struct pmu_gk20a *pmu); +int gk20a_init_pmu(struct pmu_gk20a *pmu); +void pmu_dump_falcon_stats(struct pmu_gk20a *pmu); +void gk20a_remove_pmu_support(struct pmu_gk20a *pmu); +void pmu_setup_hw(struct work_struct *work); +void pmu_seq_init(struct pmu_gk20a *pmu); #endif /*__PMU_GK20A_H__*/ -- cgit v1.2.2