From 8a64eea483d18ce603b049d5485e9f7a742da30b Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 26 Mar 2018 11:42:42 -0700 Subject: gpu: nvgpu: fix priv error register reads Current code does not compute priv error register offsets properly. This leads to invalid decoding of priv errors, and can also trigger additional priv errors. - add GPU_LIT_GPC_PRIV_STRIDE define - return proj_gpc_priv_stride for GPU_LIT_GPC_PRIV_STRIDE in hals - use GPU_LIT_GPC_PRIV_STRIDE instead of GPU_LIT_GPC_STRIDE in g->ops.priv_ring.isr() to compute priv error register offsets. Bug 2093058 Change-Id: Ia7c36ccba0441126784bb0e00452f2cf1196ef71 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1682118 Reviewed-by: svc-mobile-coverity Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f64a2b96..95736d30 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -141,6 +141,7 @@ enum gk20a_cbc_op { #define GPU_LIT_GPFIFO_CLASS 34 #define GPU_LIT_I2M_CLASS 35 #define GPU_LIT_DMA_COPY_CLASS 36 +#define GPU_LIT_GPC_PRIV_STRIDE 37 #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 1d764ad2..ed5327cb 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c @@ -58,7 +58,7 @@ void gk20a_priv_ring_isr(struct gk20a *g) u32 cmd; s32 retry = 100; u32 gpc; - u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) return; @@ -80,10 +80,10 @@ void gk20a_priv_ring_isr(struct gk20a *g) for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { if (status1 & BIT(gpc)) { gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride)); + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_priv_stride)); } } /* clear interrupt */ -- cgit v1.2.2