From 3df619f68afa6b23a33d7da072315755de38a30b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 6 Mar 2018 13:25:11 -0800 Subject: gpu: nvgpu: hal for syncpt_incr_per_release Create hal to indicate syncpt increments per release. Legacy chip uses 2 syncpt increments per release and gv1xx onwards uses 1 syncpt increment per release. Bug 2066025 Change-Id: I5d6d0a5368ef561f8150fbb7120181f49f6e338b Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1669817 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c | 5 +++-- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 5 +++++ drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + 4 files changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c index 85c55955..45d9ae9c 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Channel Synchronization Abstraction * - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -194,7 +194,8 @@ static int __gk20a_channel_syncpt_incr(struct gk20a_channel_sync *s, c->g->ops.fifo.add_syncpt_incr_cmd(c->g, wfi_cmd, incr_cmd, sp->id, sp->syncpt_buf.gpu_va); - thresh = nvgpu_nvhost_syncpt_incr_max_ext(sp->nvhost_dev, sp->id, 2); + thresh = nvgpu_nvhost_syncpt_incr_max_ext(sp->nvhost_dev, sp->id, + c->g->ops.fifo.get_syncpt_incr_per_release()); if (register_irq) { struct channel_gk20a *referenced = gk20a_channel_get(c); diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 96317520..0def724d 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -3999,6 +3999,11 @@ u32 gk20a_fifo_get_syncpt_wait_cmd_size(void) return 4; } +u32 gk20a_fifo_get_syncpt_incr_per_release(void) +{ + return 2; +} + void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g, bool wfi_cmd, struct priv_cmd_entry *cmd, u32 id, u64 gpu_va) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index a925b1e2..8a3bd4b9 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -406,6 +406,7 @@ void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g, struct priv_cmd_entry *cmd, u32 off, u32 id, u32 thresh, u64 gpu_va); u32 gk20a_fifo_get_syncpt_wait_cmd_size(void); +u32 gk20a_fifo_get_syncpt_incr_per_release(void); void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g, bool wfi_cmd, struct priv_cmd_entry *cmd, u32 id, u64 gpu_va); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4ebdb6a4..ea55c664 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -631,6 +631,7 @@ struct gpu_ops { u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd); int (*get_sync_ro_map)(struct vm_gk20a *vm, u64 *base_gpuva, u32 *sync_size); + u32 (*get_syncpt_incr_per_release)(void); #endif } fifo; struct pmu_v { -- cgit v1.2.2