From f187e0bf442c3b0a08c46b21196f06a18c8220a0 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Wed, 29 Aug 2018 12:32:25 -0700 Subject: gpu: nvgpu: Move SM_MASK_TYPE setting to TSG level Moved the SM_MASK_TYPE variable from GR to TSG struct. SM error registers are context based. In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel code iterate the TSG associated with first channel and set the mask_type to that context. Bug 200412641 Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1809322 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/tsg_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 624ee1d7..506d4330 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c @@ -304,6 +304,7 @@ struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid) tsg->timeslice_scale = 0; tsg->runlist_id = ~0; tsg->tgid = pid; + tsg->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; if (g->ops.fifo.init_eng_method_buffers) g->ops.fifo.init_eng_method_buffers(g, tsg); @@ -373,6 +374,7 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) release_used_tsg(&g->fifo, tsg); tsg->runlist_id = ~0; + tsg->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; nvgpu_log(g, gpu_dbg_fn, "tsg released %d\n", tsg->tsgid); } -- cgit v1.2.2