From 82c0c96290602b1baf296133c7f55ae1848e433a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 22 Jun 2017 12:58:43 -0700 Subject: gpu: nvgpu: Remove gk20a support Remove gk20a support. Leave only gk20a code which is reused by other GPUs. JIRA NVGPU-38 Change-Id: I3d5f2bc9f71cd9f161e64436561a5eadd5786a3b Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master/r/1507927 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 137 +-------------------------------- 1 file changed, 1 insertion(+), 136 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/regops_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index 9919fc3d..aee8677c 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c @@ -1,7 +1,7 @@ /* * Tegra GK20A GPU Debugger Driver Register Ops * - * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -729,138 +729,3 @@ bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset) regop_bsearch_range_cmp); return valid; } - -static const struct regop_offset_range *gk20a_get_global_whitelist_ranges(void) -{ - return gk20a_global_whitelist_ranges; -} - -static int gk20a_get_global_whitelist_ranges_count(void) -{ - return gk20a_global_whitelist_ranges_count; -} - -static const struct regop_offset_range *gk20a_get_context_whitelist_ranges(void) -{ - return gk20a_context_whitelist_ranges; -} - -static int gk20a_get_context_whitelist_ranges_count(void) -{ - return gk20a_context_whitelist_ranges_count; -} - -static const u32 *gk20a_get_runcontrol_whitelist(void) -{ - return gk20a_runcontrol_whitelist; -} - -static int gk20a_get_runcontrol_whitelist_count(void) -{ - return gk20a_runcontrol_whitelist_count; -} - -static const -struct regop_offset_range *gk20a_get_runcontrol_whitelist_ranges(void) -{ - return gk20a_runcontrol_whitelist_ranges; -} - -static int gk20a_get_runcontrol_whitelist_ranges_count(void) -{ - return gk20a_runcontrol_whitelist_ranges_count; -} - -static const u32 *gk20a_get_qctl_whitelist(void) -{ - return gk20a_qctl_whitelist; -} - -static int gk20a_get_qctl_whitelist_count(void) -{ - return gk20a_qctl_whitelist_count; -} - -static const struct regop_offset_range *gk20a_get_qctl_whitelist_ranges(void) -{ - return gk20a_qctl_whitelist_ranges; -} - -static int gk20a_get_qctl_whitelist_ranges_count(void) -{ - return gk20a_qctl_whitelist_ranges_count; -} - -static int gk20a_apply_smpc_war(struct dbg_session_gk20a *dbg_s) -{ - /* The following regops are a hack/war to make up for the fact that we - * just scribbled into the ctxsw image w/o really knowing whether - * it was already swapped out in/out once or not, etc. - */ - struct nvgpu_dbg_gpu_reg_op ops[4]; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(ops); i++) { - ops[i].op = REGOP(WRITE_32); - ops[i].type = REGOP(TYPE_GR_CTX); - ops[i].status = REGOP(STATUS_SUCCESS); - ops[i].value_hi = 0; - ops[i].and_n_mask_lo = 0; - ops[i].and_n_mask_hi = 0; - } - - /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/ - ops[0].offset = 0x00419e08; - ops[0].value_lo = 0x1d; - - /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */ - ops[1].offset = 0x00419e58; - ops[1].value_lo = 0x1; - - /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */ - ops[2].offset = 0x00419e68; - ops[2].value_lo = 0xaaaa; - - /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */ - ops[3].offset = 0x00419f40; - ops[3].value_lo = 0x18; - - return dbg_s->g->ops.dbg_session_ops.exec_reg_ops(dbg_s, ops, - ARRAY_SIZE(ops)); -} - -void gk20a_init_regops(struct gpu_ops *gops) -{ - gops->regops.get_global_whitelist_ranges = - gk20a_get_global_whitelist_ranges; - gops->regops.get_global_whitelist_ranges_count = - gk20a_get_global_whitelist_ranges_count; - - gops->regops.get_context_whitelist_ranges = - gk20a_get_context_whitelist_ranges; - gops->regops.get_context_whitelist_ranges_count = - gk20a_get_context_whitelist_ranges_count; - - gops->regops.get_runcontrol_whitelist = - gk20a_get_runcontrol_whitelist; - gops->regops.get_runcontrol_whitelist_count = - gk20a_get_runcontrol_whitelist_count; - - gops->regops.get_runcontrol_whitelist_ranges = - gk20a_get_runcontrol_whitelist_ranges; - gops->regops.get_runcontrol_whitelist_ranges_count = - gk20a_get_runcontrol_whitelist_ranges_count; - - gops->regops.get_qctl_whitelist = - gk20a_get_qctl_whitelist; - gops->regops.get_qctl_whitelist_count = - gk20a_get_qctl_whitelist_count; - - gops->regops.get_qctl_whitelist_ranges = - gk20a_get_qctl_whitelist_ranges; - gops->regops.get_qctl_whitelist_ranges_count = - gk20a_get_qctl_whitelist_ranges_count; - - gops->regops.apply_smpc_war = - gk20a_apply_smpc_war; -} -- cgit v1.2.2