From ed65f1f26e2d0ca4a491215297b61d25b0c1493b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 24 May 2018 12:31:57 -0700 Subject: gpu: nvgpu: Move setting priv interrupt to priv_ring Registers to set priv interrupts are in priv_ring, but the code was in bus HAL. Move the code and related HALs to priv_ring instead. JIRA NVGPU-588 Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730889 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index dea42b55..adbaf94f 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c @@ -32,6 +32,7 @@ #include #include #include +#include void gk20a_enable_priv_ring(struct gk20a *g) { @@ -103,3 +104,14 @@ void gk20a_priv_ring_isr(struct gk20a *g) if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v()) nvgpu_warn(g, "priv ringmaster intr ack too many retries"); } + +void gk20a_priv_set_timeout_settings(struct gk20a *g) +{ + /* + * Bug 1340570: increase the clock timeout to avoid potential + * operation failure at high gpcclk rate. Default values are 0x400. + */ + nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800); + nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800); + nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800); +} -- cgit v1.2.2