From d65a93b80c60bb677fbc13b7180e0f31b7f97f84 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Thu, 9 Apr 2015 16:47:13 +0530 Subject: gpu: nvgpu: add secure gpccs boot support bug 200080684 keeping it disabled by default also trimming the code by removing redundant variable to check recovery. pmu quick wait now checks only for irqs which are serviced by kernel. requests pmu to bit bang gpccs ucode. Change-Id: I12ef23d6d59b507e86a129b69eab65b21d0438c6 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/729622 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 6313b9d5..2456c784 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -3333,12 +3333,16 @@ int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, struct gk20a *g = gk20a_from_pmu(pmu); unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); unsigned long delay = GR_IDLE_CHECK_DEFAULT; + u32 servicedpmuint; + servicedpmuint = pwr_falcon_irqstat_halt_true_f() | + pwr_falcon_irqstat_exterr_true_f() | + pwr_falcon_irqstat_swgen0_true_f(); do { if (*var == val) return 0; - if (gk20a_readl(g, pwr_falcon_irqstat_r())) + if (gk20a_readl(g, pwr_falcon_irqstat_r()) & servicedpmuint) gk20a_pmu_isr(g); usleep_range(delay, delay * 2); @@ -4042,8 +4046,6 @@ int gk20a_pmu_destroy(struct gk20a *g) pmu->zbc_ready = false; g->ops.pmu.lspmuwprinitdone = false; g->ops.pmu.fecsbootstrapdone = false; - g->ops.pmu.fecsrecoveryinprogress = 0; - gk20a_dbg_fn("done"); return 0; -- cgit v1.2.2