From 01e61860fafbc0ee045c2db931a79f6c0d5300aa Mon Sep 17 00:00:00 2001 From: Peter Boonstoppel Date: Fri, 7 Oct 2016 15:30:59 -0700 Subject: gpu: nvgpu: gm20b expose gpcclk through CCF Register gpcclk with Common Clock Framework to expose GPCPLL frequency control Bug 200233943 Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e Signed-off-by: Peter Boonstoppel Reviewed-on: http://git-master/r/1236979 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/platform_gk20a.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/platform_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h index 94b8d157..f13a11ea 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h @@ -179,6 +179,8 @@ struct gk20a_platform { int (*clk_set_rate)(struct device *dev, unsigned long rate); + /* Called to register GPCPLL with common clk framework */ + int (*clk_register)(struct gk20a *g); /* Postscale callback is called after frequency change */ void (*postscale)(struct device *dev, -- cgit v1.2.2