From 9812bd5eea1c5d2c97149d64c5ccf81eae75fda1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 17 Dec 2015 10:12:21 -0800 Subject: gpu: nvgpu: Control comptagline assignment from kernel On Maxwell comptaglines are assigned per 128k, but preferred big page size for graphics is 64k. Bit 16 of GPU VA is used for determining which half of comptagline is used. This creates problems if user space wants to map a page multiple times and to arbitrary GPU VA. In one mapping the page might be mapped to lower half of 128k comptagline, and in another mapping the page might be mapped to upper half. Turn on mode where MSB of comptagline in PTE is used instead of bit 16 for determining the comptagline lower/upper half selection. Bug 1704834 Change-Id: If87e8f6ac0fc9c5624e80fa1ba2ceeb02781355b Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/924322 Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/mm_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 6c4637e8..76c33512 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -414,6 +414,10 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) gk20a_dbg_fn(""); g->ops.fb.set_mmu_page_size(g); + if (g->ops.fb.set_use_full_comp_tag_line) + mm->use_full_comp_tag_line = + g->ops.fb.set_use_full_comp_tag_line(g); + inst_pa = (u32)(inst_pa >> bar1_instance_block_shift_gk20a()); gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); @@ -2327,6 +2331,11 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, gmmu_pte_kind_f(kind_v) | gmmu_pte_comptagline_f((u32)(*ctag / ctag_granularity)); + if (vm->mm->use_full_comp_tag_line && *iova & 0x10000) { + pte_w[1] |= gmmu_pte_comptagline_f( + 1 << (gmmu_pte_comptagline_s() - 1)); + } + if (rw_flag == gk20a_mem_flag_read_only) { pte_w[0] |= gmmu_pte_read_only_true_f(); pte_w[1] |= -- cgit v1.2.2