From 7d917f43a5a8abc41988e606ef5e7311dcf23ff8 Mon Sep 17 00:00:00 2001 From: Kevin Huang Date: Fri, 23 May 2014 13:45:57 -0700 Subject: gpu: nvgpu: gm20b: fix compression sharing For GM20B alone, the LTC count is already accounted for the HW logic for the CBC base calculation from the postDivide address. So SW doesn't have to explicity divide it by the LTC count in the postDivide address calculation. Bug 1477079 Change-Id: I558bbe66bbcfb7edfa21210d0dc22c6170149260 Signed-off-by: Kevin Huang Reviewed-on: http://git-master/r/414264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/ltc_common.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gk20a/ltc_common.c') diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c index 72477983..75530b25 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_common.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c @@ -291,7 +291,7 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) compbit_base_post_divide64 = compbit_store_base_iova >> ltc_ltcs_ltss_cbc_base_alignment_shift_v(); - do_div(compbit_base_post_divide64, gr->num_fbps); + do_div(compbit_base_post_divide64, g->ltc_count); compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * @@ -300,6 +300,11 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) if (compbit_base_post_multiply64 < compbit_store_base_iova) compbit_base_post_divide++; + /* Bug 1477079 indicates sw adjustment on the posted divided base. */ + if (g->ops.ltc.cbc_fix_config) + compbit_base_post_divide = + g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); + gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), compbit_base_post_divide); -- cgit v1.2.2