From ab93322b25c9dd6058fac6523f41571d77eeaeb9 Mon Sep 17 00:00:00 2001 From: sujeet baranwal Date: Mon, 28 Sep 2015 15:26:23 -0700 Subject: gpu: nvgpu: Add CDE bits in FECS header In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B aligned, otherwise causes a HW deadlock. Gpu driver makes changes in FECS header which FECS uses to configure the T1 promotions to aligned 128B accesses. Bug 200096226 Change-Id: I8a8deaf6fb91f4bbceacd491db7eb6f7bca5001b Signed-off-by: sujeet baranwal Reviewed-by: Terje Bergstrom Signed-off-by: sujeet baranwal Reviewed-on: http://git-master/r/804625 Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h index 3d9095a8..4e3fae13 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, -- cgit v1.2.2