From f36e2a234b39cf7622c57ad51359629f5c425340 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 6 Jun 2017 15:47:17 -0700 Subject: gpu: nvgpu: support context regoptype for egpc/etpc - add is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops - add gr ops for decode and create egpc/etpc priv addr - add etpc as part of ctxsw_regs JIRA GPUT19X-49 Bug 200311674 Bug 1960226 Signed-off-by: Seema Khowala Change-Id: I9a8be1804a9354238de2441093b3b136321b7e53 Reviewed-on: https://git-master.nvidia.com/r/1522442 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h index b89124d6..535977f9 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h @@ -237,6 +237,8 @@ enum ctxsw_addr_type { CTXSW_ADDR_TYPE_PPC = 4, CTXSW_ADDR_TYPE_LTCS = 5, CTXSW_ADDR_TYPE_FBPA = 6, + CTXSW_ADDR_TYPE_EGPC = 7, + CTXSW_ADDR_TYPE_ETPC = 8, }; #define PRI_BROADCAST_FLAGS_NONE 0 @@ -247,5 +249,7 @@ enum ctxsw_addr_type { #define PRI_BROADCAST_FLAGS_LTCS BIT(4) #define PRI_BROADCAST_FLAGS_LTSS BIT(5) #define PRI_BROADCAST_FLAGS_FBPA BIT(6) +#define PRI_BROADCAST_FLAGS_EGPC BIT(7) +#define PRI_BROADCAST_FLAGS_ETPC BIT(8) #endif /* GR_PRI_GK20A_H */ -- cgit v1.2.2