From f0a9ce0469314711ddb5a8baf6bf88615b71c59e Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Thu, 25 Jun 2015 15:40:12 -0700 Subject: gpu: nvgpu: SM/TEX exception handling support Add TEX exception handling support. Also make SM exception handler into a function pointer, which should allow different chips to implement their own SM exception handling routine. Bug 1635727 Bug 1637486 Change-Id: I429905726c1840c11e83780843d82729495dc6a5 Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/935329 --- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index ad197228..9c37fd02 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -528,6 +528,10 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index); int gr_gk20a_wait_idle(struct gk20a *g, unsigned long end_jiffies, u32 expect_delay); +int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch); +int gr_gk20a_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event); int gr_gk20a_init_ctx_state(struct gk20a *g); int gr_gk20a_submit_fecs_method_op(struct gk20a *g, struct fecs_method_op_gk20a op, -- cgit v1.2.2