From a09b9cd587d27a3ef6479a17631c3497d447e7a9 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Thu, 24 May 2018 14:00:19 -0700 Subject: gpu: nvgpu: Add IOCTL for SM_EXCEPTION_TYPE_MASK Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is added to dbg session. Currently support SM_EXCEPTION_TYPE_MASK_FATAL type If this type is set then the code will skip RC recovery, instead trigger CILP preemption. bug 200412641 JIRA NVGPU-702 Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1729792 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 0c6be57b..804e0e25 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -437,6 +437,12 @@ struct gr_gk20a { u32 no_of_sm; struct sm_info *sm_to_cluster; struct nvgpu_gr_sm_error_state *sm_error_states; + +#define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) +#define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) + u32 sm_exception_mask_type; + u32 sm_exception_mask_refcount; + #if defined(CONFIG_GK20A_CYCLE_STATS) struct nvgpu_mutex cs_lock; struct gk20a_cs_snapshot *cs_data; -- cgit v1.2.2