From 5cb995c7510e0290956a3aa221c6a77d4020b3ff Mon Sep 17 00:00:00 2001 From: Ashutosh Jain Date: Wed, 20 Jan 2016 20:06:23 +0530 Subject: gpu: nvgpu: Fix wait for sm lock down. global_esr and warp_esr are edge-triggered and are cleared in kernel isr so skip checking them when wait_for_pause is called from UMD via ioctl. Bug 1619430 Change-Id: I2ae54f23ba5c8bfaab35a476f88ccca0bbb10202 Signed-off-by: Ashutosh Jain Reviewed-on: http://git-master/r/935808 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Cory Perry Tested-by: Cory Perry GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index c58daefa..ad197228 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -517,7 +517,8 @@ void gk20a_suspend_single_sm(struct gk20a *g, void gk20a_suspend_all_sms(struct gk20a *g, u32 global_esr_mask, bool check_errors); int gk20a_gr_lock_down_sm(struct gk20a *g, - u32 gpc, u32 tpc, u32 global_esr_mask); + u32 gpc, u32 tpc, u32 global_esr_mask, + bool check_errors); int gr_gk20a_set_sm_debug_mode(struct gk20a *g, struct channel_gk20a *ch, u64 sms, bool enable); bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch); -- cgit v1.2.2