From 2328d305b7c9437aa467922086b9fcfc0a4169ba Mon Sep 17 00:00:00 2001 From: Amulya Date: Mon, 6 Aug 2018 10:37:32 +0530 Subject: gpu: nvgpu: MISRA 10.4 enum fixes MISRA rule-10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3 Signed-off-by: Amulya Reviewed-on: https://git-master.nvidia.com/r/1792852 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 804e0e25..2b31b6b6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -70,6 +70,8 @@ struct tsg_gk20a; struct channel_gk20a; struct nvgpu_warpstate; +enum ctxsw_addr_type; + enum /* global_ctx_buffer */ { CIRCULAR = 0, PAGEPOOL = 1, @@ -842,7 +844,7 @@ int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map, u32 *count, u32 *offset, u32 max_cnt, u32 base, u32 mask); int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, - int *addr_type, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags); int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr, @@ -856,7 +858,7 @@ void gr_gk20a_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr, u32 num_fbpas, u32 *priv_addr_table, u32 *t); int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g, - int addr_type, u32 num_tpcs, u32 num_ppcs, + enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs, u32 reg_list_ppc_count, u32 *__offset_in_segment); void gk20a_gr_destroy_ctx_buffer(struct gk20a *g, -- cgit v1.2.2