From 1ab0eec6eae303fa2b2f7cc97b78aed4a9f895e5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 16:43:31 -0700 Subject: gpu: nvgpu: add resume_single_sm gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512216 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 90abcf22..659b37a6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -612,8 +612,8 @@ void gr_gk20a_load_ctxsw_ucode_boot(struct gk20a *g, u64 addr_base, void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c); int gr_gk20a_disable_ctxsw(struct gk20a *g); int gr_gk20a_enable_ctxsw(struct gk20a *g); -void gk20a_resume_single_sm(struct gk20a *g, - u32 gpc, u32 tpc); +void gk20a_gr_resume_single_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); void gk20a_resume_all_sms(struct gk20a *g); void gk20a_gr_suspend_single_sm(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, -- cgit v1.2.2