From d6b5d74c5ede5fb620b056286f9f615566f84b29 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 26 Feb 2018 17:58:14 -0800 Subject: gpu: nvgpu: make gr functions that are used by vsrv global Fixed vsrv link errors for gr unification. Jira VQRM-2982 Change-Id: Icd46792191f1a9aaefbf86d2f3c0b4d5bce2384e Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1664706 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index c64900bd..07185db2 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -752,7 +752,7 @@ static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) gr_fecs_current_ctx_valid_f(1); } -static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, +int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, struct channel_gk20a *c) { u32 inst_base_ptr = u64_lo32(nvgpu_inst_block_addr(g, &c->inst_block) @@ -881,7 +881,7 @@ u32 gk20a_gr_tpc_offset(struct gk20a *g, u32 tpc) return tpc_offset; } -static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g, +int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g, struct channel_gk20a *c, bool patch) { struct gr_gk20a *gr = &g->gr; @@ -1282,7 +1282,7 @@ int gr_gk20a_init_fs_state(struct gk20a *g) return 0; } -static int gr_gk20a_fecs_ctx_image_save(struct channel_gk20a *c, u32 save_type) +int gr_gk20a_fecs_ctx_image_save(struct channel_gk20a *c, u32 save_type) { struct gk20a *g = c->g; int ret; @@ -1306,7 +1306,7 @@ static int gr_gk20a_fecs_ctx_image_save(struct channel_gk20a *c, u32 save_type) return ret; } -static u32 gk20a_init_sw_bundle(struct gk20a *g) +u32 gk20a_init_sw_bundle(struct gk20a *g) { struct av_list_gk20a *sw_bundle_init = &g->gr.ctx_vars.sw_bundle_init; u32 last_bundle_data = 0; -- cgit v1.2.2