From b026c012963b135f8689c4409d12e79a76bb1156 Mon Sep 17 00:00:00 2001 From: Anup Mahindre Date: Wed, 5 Sep 2018 17:36:46 +0530 Subject: gpu: nvgpu: Return gr_ctx_resident from NVGPU_DBG_GPU_IOCTL_REG_OPS NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was resident in engine or not. Regops are broken down into batches of 128 and each batch is executed together. Since there only 32 bits were available in IOCTL args, returning is ctx was resident isn't possible for all batches. Hence return if the ctx was resident for the first batch. Bug 200445575 Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af Signed-off-by: Anup Mahindre Reviewed-on: https://git-master.nvidia.com/r/1812975 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index a40d93fd..f3b580e4 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -8358,7 +8358,8 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, - u32 num_ctx_wr_ops, u32 num_ctx_rd_ops) + u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, + bool *is_curr_ctx) { struct gk20a *g = ch->g; int err, tmp_err; @@ -8376,7 +8377,9 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, } ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch); - + if (is_curr_ctx != NULL) { + *is_curr_ctx = ch_is_curr_ctx; + } nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d", ch_is_curr_ctx); @@ -8694,7 +8697,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g, i++; } - err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0); + err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL); if (err) { nvgpu_err(g, "Failed to access register"); } -- cgit v1.2.2