From ac687c95d383c3fb0165e6535893510409559a8e Mon Sep 17 00:00:00 2001 From: Vinod G Date: Wed, 16 May 2018 10:43:13 -0700 Subject: gpu: nvgpu: Code updates for MISRA violations Code related to MC module is updated for handling MISRA violations Rule 10.1: Operands shalln't be an inappropriate essential type. Rule 10.3: Value of expression shalln't be assigned to an object with a narrow essential type. Rule 10.4: Both operands in an operator shall have the same essential type. Rule 14.4: Controlling if statement shall have essentially Boolean type. Rule 15.6: Enclose if() sequences with braces. JIRA NVGPU-646 JIRA NVGPU-659 JIRA NVGPU-671 Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1720926 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index c7d028b2..5fd0eb0c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -6134,18 +6134,18 @@ int gk20a_gr_isr(struct gk20a *g) return 0; } -int gk20a_gr_nonstall_isr(struct gk20a *g) +u32 gk20a_gr_nonstall_isr(struct gk20a *g) { - int ops = 0; + u32 ops = 0; u32 gr_intr = gk20a_readl(g, gr_intr_nonstall_r()); nvgpu_log(g, gpu_dbg_intr, "pgraph nonstall intr %08x", gr_intr); - if (gr_intr & gr_intr_nonstall_trap_pending_f()) { + if ((gr_intr & gr_intr_nonstall_trap_pending_f()) != 0U) { /* Clear the interrupt */ gk20a_writel(g, gr_intr_nonstall_r(), gr_intr_nonstall_trap_pending_f()); - ops |= (gk20a_nonstall_ops_wakeup_semaphore | + ops |= (u32)(gk20a_nonstall_ops_wakeup_semaphore | gk20a_nonstall_ops_post_events); } return ops; -- cgit v1.2.2