From 2aead8a72fbe31b5bb99fde54e496752ab224c2d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 5 Aug 2015 11:00:39 -0700 Subject: gpu: nvgpu: Disable only channel at zcull bind At zcull bind we disable whole GR engine. This is unnecessary, so instead disable only the channel and make sure it's unloaded. Introduces also an API in fifo_gk20a.c to do the channel disable. gr_gk20a_ctx_zcull_setup() was always passed true as last parameter, so remove parameter. Change-Id: I7ae6e101ec7d1ab3f6ee4e9bcc442d23dbd21247 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/787570 --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f01b3f37..0cb18665 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -703,12 +703,9 @@ static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, return ret; } -static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c, - bool disable_fifo) +static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c) { struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; - struct fifo_gk20a *f = &g->fifo; - struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; u32 va_lo, va_hi, va; int ret = 0; void *ctx_ptr = NULL; @@ -732,30 +729,21 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c, va_hi = u64_hi32(ch_ctx->zcull_ctx.gpu_va); va = ((va_lo >> 8) & 0x00FFFFFF) | ((va_hi << 24) & 0xFF000000); - if (disable_fifo) { - ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to disable gr engine activity\n"); - goto clean_up; - } + c->g->ops.fifo.disable_channel(c); + ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid); + if (ret) { + c->g->ops.fifo.enable_channel(c); + gk20a_err(dev_from_gk20a(g), + "failed to disable gr engine activity\n"); + goto clean_up; } - g->ops.mm.fb_flush(g); - gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_o(), 0, ch_ctx->zcull_ctx.ctx_sw_mode); gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_ptr_o(), 0, va); - if (disable_fifo) { - ret = gk20a_fifo_enable_engine_activity(g, gr_info); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to enable gr engine activity\n"); - goto clean_up; - } - } + c->g->ops.fifo.enable_channel(c); clean_up: vunmap(ctx_ptr); @@ -3343,7 +3331,7 @@ int gr_gk20a_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, zcull_ctx->gpu_va = zcull_va; /* TBD: don't disable channel in sw method processing */ - return gr_gk20a_ctx_zcull_setup(g, c, true); + return gr_gk20a_ctx_zcull_setup(g, c); } int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, -- cgit v1.2.2