From fc724baa4becf051b3e6647858a6ded90f1cee86 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 7 Jun 2017 12:44:10 -0700 Subject: gpu: nvgpu: Add MC HAL is_intr1_pending Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit that is passed as parameter to is_intr1_pending. The API is passed contents of intr1 register and an engine number, and returns true if there's an interrupt pending for the engine. JIRA NVGPU-26 Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1497870 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2ede539e..bd93cc33 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -142,6 +142,8 @@ enum gk20a_cbc_op { #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) +enum nvgpu_unit; + struct gpu_ops { struct { int (*determine_L2_size_bytes)(struct gk20a *gk20a); @@ -851,6 +853,7 @@ struct gpu_ops { void (*disable)(struct gk20a *g, u32 units); void (*reset)(struct gk20a *g, u32 units); u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); + bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); } mc; struct { void (*show_dump)(struct gk20a *g, -- cgit v1.2.2