From d8c0144f8b45ef8a94fc696efaa0c782c4c787af Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 13:43:35 -0700 Subject: gpu: nvgpu: add clear_sm_hww gr ops Required for multiple SM support and t19x SM register address changes JIRA GPUT19X-75 Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514043 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 483cdd6e..95b93496 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -300,6 +300,8 @@ struct gpu_ops { u32 global_esr_mask, bool check_errors); int (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, bool check_errors); + void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, + u32 global_esr); void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); int (*handle_sm_exception)(struct gk20a *g, -- cgit v1.2.2