From c3c3a3c5715d6aa38544922b76a636135429fd22 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Feb 2017 16:53:35 -0800 Subject: gpu: nvgpu: add fifo ops for handling pbdma intr_0 This is needed to handle bit 20 (clear_faulted_error) and bit 24 (eng_reset) of t19x pbdma_intr_0 interrupt. JIRA GPUT19X-47 Change-Id: I07c603eff96344c0104579e339e5cf7f675128ef Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1306556 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e4450185..7d7d573a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -474,6 +474,9 @@ struct gpu_ops { struct mmu_fault_info *mmfault); bool (*handle_sched_error)(struct gk20a *g); bool (*handle_ctxsw_timeout)(struct gk20a *g, u32 fifo_intr); + unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_0, + u32 *handled, u32 *error_notifier); } fifo; struct pmu_v { /*used for change of enum zbc update cmd id from ver 0 to ver1*/ -- cgit v1.2.2