From a69fa0e96cb8ca253ec3468f288f410219129b9a Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 11 Jan 2017 09:53:29 +0530 Subject: nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL. pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 6ca5855a..7df2c2e0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -618,6 +618,10 @@ struct gpu_ops { int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); int (*pmu_nsbootstrap)(struct pmu_gk20a *pmu); int (*pmu_setup_elpg)(struct gk20a *g); + u32 (*pmu_get_queue_head)(u32 i); + u32 (*pmu_get_queue_head_size)(void); + u32 (*pmu_get_queue_tail_size)(void); + u32 (*pmu_get_queue_tail)(u32 i); int (*init_wpr_region)(struct gk20a *g); int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); void (*write_dmatrfbase)(struct gk20a *g, u32 addr); -- cgit v1.2.2