From 9891cb117e538f1ea5d19171a3c88422cdce7162 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 21:28:10 -0700 Subject: gpu: nvgpu: add gr ops get_sm_hww_global_esr Required for multiple SM support and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I437095cb8f8d2ba31b85594a7609532991441a37 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514040 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d45477fc..70b1ac5f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -293,6 +293,8 @@ struct gpu_ops { bool *early_exit, bool *ignore_debugger); u32 (*get_sm_hww_warp_esr)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm); + u32 (*get_sm_hww_global_esr)(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); int (*handle_sm_exception)(struct gk20a *g, -- cgit v1.2.2