From 7f8226887c28267d3c2351692d4429ead1e17695 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 29 Aug 2018 15:46:12 -0400 Subject: gpu: nvgpu: cleanup return types for MISRA 10.3 This is a big cleanup of return types across a number of modules in the nvgpu driver. Many functions were returning u32 but using negative return codes. This is a MISRA 10.3 violation by assigning signed values to a u32. JIRA NVGPU-647 Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1810743 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2b8e8b0a..c98fec48 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -850,14 +850,15 @@ struct gpu_ops { void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg, u8 value); struct { - u32 (*boardobjgrp_pmucmd_construct_impl)(struct gk20a *g, + int (*boardobjgrp_pmucmd_construct_impl) + (struct gk20a *g, struct boardobjgrp *pboardobjgrp, struct boardobjgrp_pmu_cmd *cmd, u8 id, u8 msgid, u8 hdrsize, u8 entrysize, u16 fbsize, u32 ss_offset, u8 rpc_func_id); - u32 (*boardobjgrp_pmuset_impl)(struct gk20a *g, + int (*boardobjgrp_pmuset_impl)(struct gk20a *g, struct boardobjgrp *pboardobjgrp); - u32 (*boardobjgrp_pmugetstatus_impl)(struct gk20a *g, + int (*boardobjgrp_pmugetstatus_impl)(struct gk20a *g, struct boardobjgrp *pboardobjgrp, struct boardobjgrpmask *mask); int (*is_boardobjgrp_pmucmd_id_valid)(struct gk20a *g, -- cgit v1.2.2