From 791ce6bd5480a8393c12be55e8afa459cb4dd1ff Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 23 Jan 2018 12:16:40 -0800 Subject: gpu: nvgpu: gv11b: enable more gr exceptions -pd, scc, ds, ssync, mme and sked exceptions are enabled. This will be useful for debugging -Handle enabled interrupts -Add gr ops to handle ssync hww. For legacy chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr. Since ssync hww is not enabled on legacy chips, added ssync hww exception handling for volta only. Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1644751 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3bc10109..5e46344a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -442,6 +442,7 @@ struct gpu_ops { void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); void (*fecs_host_int_enable)(struct gk20a *g); + int (*handle_ssync_hww)(struct gk20a *g); } gr; struct { void (*init_hw)(struct gk20a *g); -- cgit v1.2.2