From 74639b444251d7adc222400625eb59a3d53d0c0a Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 22 Aug 2018 09:57:01 +0530 Subject: gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL In nvgpu repository, we have multiple accesses to methods in pmu_gk20a.h which have register accesses. Instead of directly invoking these methods, these are now called via HALs. Some common methods such as pmu_wait_message_cond which donot have any register accesses are moved to pmu_ipc.c and the method declarations are moved to pmu.h. Also, changed gm20b_pmu_dbg to nvgpu_dbg_pmu all across the code base. This would remove all indirect dependencies via gk20a.h into pmu_gk20a.h. As a result pmu_gk20a.h is now removed from gk20a.h JIRA-597 Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080 Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1804283 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 192f4c3e..5a888303 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -68,7 +68,6 @@ struct nvgpu_ctxsw_trace_filter; #include "ce2_gk20a.h" #include "fifo_gk20a.h" #include "tsg_gk20a.h" -#include "pmu_gk20a.h" #include "clk/clk.h" #include "perf/perf.h" #include "pmgr/pmgr.h" @@ -1025,6 +1024,15 @@ struct gpu_ops { u32 id, u32 *token); int (*pmu_mutex_release)(struct nvgpu_pmu *pmu, u32 id, u32 *token); + bool (*pmu_is_interrupted)(struct nvgpu_pmu *pmu); + void (*pmu_isr)(struct gk20a *g); + void (*pmu_init_perfmon_counter)(struct gk20a *g); + void (*pmu_pg_idle_counter_config)(struct gk20a *g, u32 pg_engine_id); + u32 (*pmu_read_idle_counter)(struct gk20a *g, u32 counter_id); + void (*pmu_reset_idle_counter)(struct gk20a *g, u32 counter_id); + void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu); + void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu); + void (*pmu_enable_irq)(struct nvgpu_pmu *pmu, bool enable); int (*init_wpr_region)(struct gk20a *g); int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); void (*write_dmatrfbase)(struct gk20a *g, u32 addr); -- cgit v1.2.2