From 67a41e46a230cde7353e4cd46040f1e71d7cd289 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 13 May 2016 07:56:43 -0700 Subject: gpu: nvgpu: Read all fields of device_info We were not using the engine_type field in device info, and the code did not handle chained entries properly. The code assumed that first entry is for graphics and second for CE, which is not always true. Improve the code to go through all entries of device_info, and preserve values across entries until we reach the last entry. Only last entry triggers a write to fifo engine info. There can also be multiple engines with same type, so accumulate interrupts and reset ids from all of them. As the code got fixed, now it reads the engine enum correctly from hardware. We used to compare that against CE0, but we should compare against CE2. gk20a_fifo_reset_engine() uses wrong constants - it is passed a internal numbering of engines, but it compares them against hardware engine enum. Change-Id: Ia59273921c602d2a090f7a5b1404afb0fca2532c Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1147746 Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 5d06a441..d5310b02 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -330,6 +330,7 @@ struct gpu_ops { int (*channel_set_timeslice)(struct channel_gk20a *ch, u32 timeslice); int (*force_reset_ch)(struct channel_gk20a *ch, bool verbose); + int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type); } fifo; struct pmu_v { /*used for change of enum zbc update cmd id from ver 0 to ver1*/ -- cgit v1.2.2