From 5570194dc4d97a857b354b706949e27663ebeee0 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 12 May 2017 11:01:10 -0700 Subject: gpu: nvgpu: per-chip GPCCS exception support Adding support for ISR handling of GPCCS exceptions JIRA: GPUT19X-83 Change-Id: Ia5550aac8f368d8915f6c94aa22478cacbb2bddc Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1480992 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index b3292ac4..3d1e0847 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -309,6 +309,8 @@ struct gpu_ops { u32 *hww_global_esr); int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event); + int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc, + u32 gpc_exception); void (*enable_gpc_exceptions)(struct gk20a *g); void (*create_gr_sysfs)(struct device *dev); u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); @@ -749,6 +751,8 @@ struct gpu_ops { u32 lspmuwprinitdone; u32 lsfloadedfalconid; bool fecsbootstrapdone; + void (*handle_ext_irq)(struct gk20a *g, u32 intr); + void (*set_irqmask)(struct gk20a *g); } pmu; struct { void (*disable_slowboot)(struct gk20a *g); -- cgit v1.2.2