From 4022b989aa2e91fe77ed52df49d45838f6d8b9bb Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 23 Mar 2017 11:03:15 -0700 Subject: gpu: nvgpu: Remove direct HW access from ctrl_gk20a.c ctrl_gk20a.c had some direct accesses to hardware. These violate the HAL rules, because we don't have per-GPU ctrl, and thus the code cannot be made GPU independent. Move all GR accesses to new GR HALs and use existing bus HAL for accessing timer. Remove #includes of all hardware headers. JIRA NVGPU-28 Change-Id: I57e67519f62e9bd6c3e725e1bef6e366190f5834 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1327001 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4f50ae36..951c8267 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -346,6 +346,12 @@ struct gpu_ops { struct mem_desc *mem, u64 gpu_va); void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); void (*load_tpc_mask)(struct gk20a *g); + int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); + int (*trigger_suspend)(struct gk20a *g); + int (*wait_for_pause)(struct gk20a *g, struct warpstate *w_state); + int (*resume_from_pause)(struct gk20a *g); + int (*clear_sm_errors)(struct gk20a *g); + u32 (*tpc_enabled_exceptions)(struct gk20a *g); } gr; struct { void (*init_hw)(struct gk20a *g); -- cgit v1.2.2