From 2328d305b7c9437aa467922086b9fcfc0a4169ba Mon Sep 17 00:00:00 2001 From: Amulya Date: Mon, 6 Aug 2018 10:37:32 +0530 Subject: gpu: nvgpu: MISRA 10.4 enum fixes MISRA rule-10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3 Signed-off-by: Amulya Reviewed-on: https://git-master.nvidia.com/r/1792852 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c29c03f0..204fd371 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -250,7 +250,7 @@ struct gpu_ops { int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr, struct gr_zcull_info *zcull_params); int (*decode_egpc_addr)(struct gk20a *g, - u32 addr, int *addr_type, + u32 addr, enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); void (*egpc_etpc_priv_addr_table)(struct gk20a *g, u32 addr, u32 gpc, u32 tpc, u32 broadcast_flags, @@ -473,7 +473,7 @@ struct gpu_ops { u32 *count, u32 *offset, u32 max_cnt, u32 base, u32 mask); int (*decode_priv_addr)(struct gk20a *g, u32 addr, - int *addr_type, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags); @@ -495,8 +495,9 @@ struct gpu_ops { struct channel_gk20a *c, bool patch); u32 (*get_nonpes_aware_tpc)(struct gk20a *g, u32 gpc, u32 tpc); int (*get_offset_in_gpccs_segment)(struct gk20a *g, - int addr_type, u32 num_tpcs, u32 num_ppcs, - u32 reg_list_ppc_count, u32 *__offset_in_segment); + enum ctxsw_addr_type addr_type, u32 num_tpcs, + u32 num_ppcs, u32 reg_list_ppc_count, + u32 *__offset_in_segment); } gr; struct { void (*init_hw)(struct gk20a *g); -- cgit v1.2.2