From 0e2e3898f7f8828ff9601d414f730b9fa8d09b3f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 15:33:42 -0700 Subject: gpu: nvgpu: add suspend_single_sm gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Id104f611736535874cdaa5a2f768f692d799c2c5 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512214 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a1ad96b9..f97534b5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -370,6 +370,9 @@ struct gpu_ops { int (*set_czf_bypass)(struct gk20a *g, struct channel_gk20a *ch); bool (*sm_debugger_attached)(struct gk20a *g); + void (*suspend_single_sm)(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, + u32 global_esr_mask, bool check_errors); } gr; struct { void (*init_hw)(struct gk20a *g); -- cgit v1.2.2