From 2f712e22303471b8dd2f9388c874d12b07aed258 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 28 Jun 2017 16:23:18 +0530 Subject: gpu: nvgpu: falcon HAL to support SEC2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Updated falcon controller HAL to support SEC2 falcon & used "is_falcon_supported" flag to know the support on chip. - Created falcon HAL “flcn_gp106.c/h” under gp106 to enable support for SEC2 & inherited gk20a flcn support. - Deleted SEC2 falcon related methods to make use of generic flacon controller methods for SEC2. - GP106 SEC2 code cleanup NVPU JIRA-99 Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1510200 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/gk20a.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 9452e153..380c28ac 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -176,6 +176,7 @@ int gk20a_finalize_poweron(struct gk20a *g) /* init interface layer support for PMU falcon */ nvgpu_flcn_sw_init(g, FALCON_ID_PMU); + nvgpu_flcn_sw_init(g, FALCON_ID_SEC2); if (g->ops.bios_init) err = g->ops.bios_init(g); -- cgit v1.2.2