From 94cb4b635fba4c01b58f36a6d3384db729e4c9f6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 15 Jun 2017 22:10:43 +0530 Subject: gpu: nvgpu: use nvgpu_flcn_* interfaces - set nvgpu_flcn_reset() to point to gk20a_pmu_reset() - set PMU interrupt using nvgpu_flcn_enable_irq() - replace pmu_idle with nvgpu_flcn_wait_idle() JIRA NVGPU-57 Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1469478 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/flcn_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 9568b979..0b140802 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c @@ -107,6 +107,25 @@ static bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn) return status; } +static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) +{ + struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = + &flcn->flcn_engine_dep_ops; + + switch (flcn->flcn_id) { + case FALCON_ID_PMU: + flcn_eng_dep_ops->reset_eng = gk20a_pmu_reset; + break; + default: + /* NULL assignment make sure + * CPU hard reset in gk20a_flcn_reset() gets execute + * if falcon doesn't need specific reset implementation + */ + flcn_eng_dep_ops->reset_eng = NULL; + break; + } +} + static void gk20a_falcon_ops(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -116,6 +135,8 @@ static void gk20a_falcon_ops(struct nvgpu_falcon *flcn) flcn_ops->is_falcon_cpu_halted = gk20a_is_falcon_cpu_halted; flcn_ops->is_falcon_idle = gk20a_is_falcon_idle; flcn_ops->is_falcon_scrubbing_done = gk20a_is_falcon_scrubbing_done; + + gk20a_falcon_engine_dependency_ops(flcn); } static void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn) -- cgit v1.2.2