From c3c3a3c5715d6aa38544922b76a636135429fd22 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Feb 2017 16:53:35 -0800 Subject: gpu: nvgpu: add fifo ops for handling pbdma intr_0 This is needed to handle bit 20 (clear_faulted_error) and bit 24 (eng_reset) of t19x pbdma_intr_0 interrupt. JIRA GPUT19X-47 Change-Id: I07c603eff96344c0104579e339e5cf7f675128ef Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1306556 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index dc43c532..70addf13 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -42,6 +42,8 @@ #define RC_TYPE_NORMAL 0 #define RC_TYPE_MMU_FAULT 1 +#define RC_TYPE_PBDMA_FAULT 2 +#define RC_TYPE_NO_RC 0xff /* * Number of entries in the kickoff latency buffer, used to calculate @@ -391,4 +393,8 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, bool *verbose, u32 *ms); bool gk20a_fifo_handle_sched_error(struct gk20a *g); +void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id, + int pbdma_method_index); +unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, + u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); #endif /*__GR_GK20A_H__*/ -- cgit v1.2.2